1 ?2016 integrated device technology, inc. march 2016 dsc 2528/18 high-speed 4k x 9dual-port static ram idt7014s functional block diagram features: true dual-ported memory cells which allow simultaneous reads of the same memory location high-speed access ? commercial: 12/15/20/25ns (max.) ? industrial: 20ns (max.) standard-power operation ? idt7014s active: 750mw (typ.) fully asynchronous operation from either port ttl-compatible; single 5v (10%) power supply available in 52-pin plcc and a 64-pin tqfp industrial temperature range (?40c to +85c) is available for selected speeds green parts available, see ordering information i/o control i/o control memory array address decoder address decoder r/ w r oe r a 0r -a 11r r/ w l oe l a 0l -a 11l i/o 0l -i/o 8l 2528 drw 01 i/o 0r -i/o 8r description: the idt7014 is a high-speed 4k x 9 dual-port static ram designed to be used in systems where on-chip hardware port arbitration is not needed. this part lends itself to high-speed applications which do not rely on busy signals to manage simultaneous access. the idt7014 provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. see functional description. the idt7014 utilitizes a 9-bit wide data path to allow for parity at the user's option. this feature is especially useful in data communication applications where it is necessary to use a parity bit for transmission/ reception error checking. fabricated using a high-performance technology, these dual-ports typically operate on only 750mw of power at maximum access times as fast as 12ns. the idt7014 is packaged in a 52-pin plcc and a 64-pin thin quad flatpack, (tqfp).
idt7014s high-speed 4k x 9 dual-port static ram industrial and commercial temperature ranges 2 pin configuration (1,2,3) notes : 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground supply. 3. j52-1 package body is approximately .75 in x .75 in. x .17 in. pn64-1 package body is approximately 14mm x 14mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate the orientation of the actual part-marking 2528 drw 02 idt 7014j j52 (4) 52-pin plcc top view (5) index a 6r a 5r a 4r a 3r a 2r a 1r a 0r a 0l a 1l a 2l a 3l a 4l a 5l 46 45 44 43 42 41 40 39 38 37 36 35 34 i/o 6l a 6l a 7l a 8l a 9l a 10l a 11l v cc i/o 7l 8 9 10 11 12 13 14 15 16 17 18 19 20 47 48 49 50 51 52 1 2 3 4 5 6 7 33 32 31 30 29 28 27 26 25 24 23 22 21 oe l r/ w l gnd i/o 8l i/o 6r i/o 5r i/o 7r gnd r/ w r gnd oe r a 11r a 10r a 8r a 7r a 9r i/o 8r i/o 5l v cc i/o 4l i/o 3l i/o 2l i/o 1l i/o 0l i/o 0r i/o 1r i/o 2r i/o 3r i/o 4r v cc index 7014 pn64 (4) 8 9 10 11 12 131415 16 1 2 3 gnd gnd 4 5 n/c n/c n/c n/c 6 7 46 45 44 43 42 41 40 39 38 37 36 35 34 47 48 33 17 18 19 20 32 31 30 29 28 27 26 25 24 23 22 21 49 50 51 52 63 62 61 60 59 58 57 56 55 54 53 64 n/c a 10l a 11l n/c r/ w l n/c gnd a 9l oe l v cc a 6l a 7l a 8l i/o 8l i/o 7l i/o 6l i/o 6r gnd a 7r a 8r a 9r a 10r a 11r n/c n/c n/c i/o 7r a 6r gnd i/o 8r r/ w r oe r 2528 drw 03 i/o 5l v cc i/o 4l i/o 3l i/o 2l i/o 1l i/o 0l i/o 0r i/o 1r i/o 2r i/o 3r v cc i/o 4r i/o 5r a 5r a 4r a 3r a 2r a 1r a 0r a 0l a 1l a 2l a 3l a 4l a 5l
6.42 idt7014s high-speed 4k x 9 dual-port static ram industrial and com mercial temperature ranges 3 absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > vcc + 10%. maximum operating temperature and supply voltage (1,2) recommended dc operating conditions notes: 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 10%. notes: 1. this is the parameter t a . this is the "instant on" case temperature. dc electrical characteristics over the operating temperature and supply voltage range (1) (v cc = 5.0v 10%) note: 1. at v cc < 2.0v input leakages are undefined. symbol rating commercial & industrial unit v te rm (2 ) terminal voltage with respect to gnd -0.5 to +7.0 v v te rm (2 ) terminal voltage -0.5 to +v cc v t bias temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c i out dc output current 50 ma 2528 tbl 01 grade ambient temperature gnd vcc commercial 0 o c to +70 o c0v 5.0v + 10% industrial -40 o c to +85 o c0v 5.0v + 10% 25 28 tb l 02 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ 6.0 (2) v v il input low voltage -0.5 (1) ____ 0.8 v 2528 tbl 03 symbol parameter test conditions 7014s unit min. max. |i li | input leakage current v cc = 5.5v, v in = 0v to v cc ___ 10 a |i lo | output leakage current v out = 0v to v cc ___ 10 a v ol output low voltage i ol = +4ma ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ v 2528 tbl 04
idt7014s high-speed 4k x 9 dual-port static ram industrial and commercial temperature ranges 4 dc electrical characteristics over the operating temperature and supply voltage range (v cc = 5v 10%) ac test conditions capacitance (1) (t a = +25c, f = 1.0mhz) tqfp package only notes: 1. this parameter is determined by device characteristics but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals swith from 0v to 3v or from 3v to 0v. figure 1. ac output test load. figure 2. output test load (for t hz , t wz , and t ow ) *including scope and jig. figure 3. typical output derating (lumped capacitive load). notes: 1. at f = fmax, address inputs are cycling at the maximum read cycle of 1/t rc using the "ac test conditions" input levels of gnd to 3v. 893 ? 30pf 347 ? data out 5v 5v 893 ? 5pf* 347 ? data out 2528 drw 05 2528 drw 04 , symbol parameter test condition version 7014s12 com'l only 7014s15 com'l only unit typ. max typ. max i cc dynamic operating current (both ports active) outputs open f = f max (1) com'l s 160 250 160 250 ma ind s ____ ____ ____ ____ 2528 tbl 05a symbol parameter test condition version 7014s20 com'l & ind 7014s25 com'l only unit typ. max typ. max. i cc dynamic operating current (both ports active) outputs open f = f max (1) com'l s 155 245 150 240 ma ind s 155 260 ____ ____ 2528 tbl 05b input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 3ns max. 1.5v 1.5v figures 1,2 and 3 2528 tbl 06 symbol parameter conditions (2) max. unit c in input capacitance v in = 3dv 9 pf c out output capacitance v out = 3dv 10 pf 2528 tbl 07 1 2 3 4 5 6 7 8 20 40 100 60 80 120 140 160 180 200 t aa (typical, ns) capacitance (pf) 2528 drw 06 -1 0 10pf is the i/o capacitance of this device, and 30pf is the ac test load capacitance ,
6.42 idt7014s high-speed 4k x 9 dual-port static ram industrial and com mercial temperature ranges 5 ac electrical characteristics over the operating temperature and supply voltage notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is determined by device characterization, but is not production tested. 7014s12 com'l only 7014s15 com'l only unit symbol parameter min.max.min.max. read cycle t rc read cycle time 12 ____ 15 ____ ns t aa address access time ____ 12 ____ 15 ns t aoe output enable access time ____ 8 ____ 8ns t oh output hold from address change 3 ____ 3 ____ ns t lz output low-z time (1,2) 3 ____ 3 ____ ns t hz output high-z time (1,2) ____ 7 ____ 7ns 2528 tbl 08a 7014s20 com'l & ind 7014s25 com'l only unit symbol parameter min.max.min.max. read cycle t rc read cycle time 20 ____ 25 ____ ns t aa address access time ____ 20 ____ 25 ns t aoe output enable access time ____ 10 ____ 12 ns t oh output hold from address change 3 ____ 3 ____ ns t lz outp ut lo w-z time (1,2) 3 ____ 3 ____ ns t hz output high-z time (1,2) ____ 9 ____ 11 ns 2528 tbl 08b
idt7014s high-speed 4k x 9 dual-port static ram industrial and commercial temperature ranges 6 timing waveform of write with port-to-port read (1,2) timing waveform of read cycle no. 1, either side (1,2) timing waveform of read cycle no. 2, either side (1, 3) notes: 1. r/ w "b" = v ih , read cycle pass through. 2. all timing is the same for left and right ports. port "a" may be either left or right port. port "b" is opposite from port "a". address data out previous data valid data valid t oh t oh t aa t rc 2528 drw 07 2528 drw 08 data out valid data t aoe oe t lz t hz notes: 1. r/ w = v ih for read cycles. 2. oe = v il . 3. addresses valid prior to oe transition low. 2528 drw 09 r/ w "a" valid t wc match valid match t wp t dw t wdd t ddd addr "a" data in "a" data out "b" addr "b" t dh
6.42 idt7014s high-speed 4k x 9 dual-port static ram industrial and com mercial temperature ranges 7 ac electrical characteristics over the operating temperature and supply voltage notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. the specification for t dh must be met by the device supplying write data to the ram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 4. port-to-port delay through ram cells from writing port to reading port, refer to ?timing waveform of write with port-to-port read?. symbol parameter 7014s12 com'l only 7014s15 com'l only unit min. max. min. max. write cycle t wc write cycle time 12 ____ 15 ____ ns t aw address valid to end-of-write 10 ____ 14 ____ ns t as address set-up time 0 ____ 0 ____ ns t wp write pulse width 10 ____ 12 ____ ns t wr write recovery time 1 ____ 1 ____ ns t dw data valid to end-of-write 8 ____ 10 ____ ns t hz output high-z time (1,2) ____ 7 ____ 7ns t dh data hold time (3) 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 7 ____ 7ns t ow output active from end-of-write (1, 2,3 ) 0 ____ 0 ____ ns t wdd write pulse to data delay (4) ____ 25 ____ 30 ns t ddd write data valid to read data delay (4) ____ 22 ____ 25 ns 2528 tbl 09a symbol parameter 7014s20 com'l & ind 7014s25 com'l only unit min. max. min. max. write cycle t wc write cycle time 20 ____ 25 ____ ns t aw address valid to end-of-write 15 ____ 20 ____ ns t as address set-up time 0 ____ 0 ____ ns t wp write pulse width 15 ____ 20 ____ ns t wr write recovery time 2 ____ 2 ____ ns t dw data valid to end-of-write 12 ____ 15 ____ ns t hz output high-z time (1,2) ____ 9 ____ 11 ns t dh data hold time (3) 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 9 ____ 11 ns t ow output active from end-of-write (1, 2,3) 0 ____ 0 ____ ns t wdd write pulse to data delay (4 ) ____ 40 ____ 45 ns t ddd write data valid to read data delay (4) ____ 30 ____ 35 ns 2528 tbl 09b
idt7014s high-speed 4k x 9 dual-port static ram industrial and commercial temperature ranges 8 truth table i ? read/write control timing waveform of write cycle (1,2,3,4,5) functional description the idt7014 provides two ports with separate control, address, and i/o pins that permit independent access for reads or writes to any location in memory. it lacks the chip enable feature of cmos dual ports, thus it operates in active mode as soon as power is applied. each port has its own output enable control ( oe ). in the read mode, the port?s oe turns on the output drivers when set low. the user application should avoid simultaneous write operations to the same memory location. there is no on-chip arbitration circuitry to resolve write priority and partial data from both ports may be written. read/write conditions are illustrated in table 1. note: 1. a ol - a 11l is not equal to a or - a 11r. 'h' = high,'l' = low, 'x' = don?t care, and 'z' = high impedance. 2528 drw 10 r/ w t wp t dw data out address data in oe t aw t as (5) t wr t dh t ow t hz (4) (3) (3) t wz (4) left or right port (1) r/ woe d 0-8 function lxdata in data written into memory hldata out data in memor y output on port x h z high-impedance outputs 2528 t bl 10 notes: 1. r/ w must be high during all address transitions. 2. t wr is measured from r/ w going high to the end of write cycle. 3. during this period, the i/o pins are in the output state, and input signals must not be applied. 4. transition is measured 0mv from the low or high-impedance voltage with the output test load (figure 2). 5. if oe is low during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe is high during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp .
6.42 idt7014s high-speed 4k x 9 dual-port static ram industrial and com mercial temperature ranges 9 ordering information datasheet document history 01/06/99: initiated datasheet document history converted to new format cosmetic and typographical corrections page 2 added additional notes to pin configurations 06/03/99: changed drawing format page 1 corrected dsc number 03/10/00: added industrial temperature ranges and deleted corresponding notes replaced idt logo page 1 made corrections to drawing changed 200mv to 0mv in notes page 6 made changes to drawings 05/19/00: page 3 increased storage temperature parameter clarified t a parameter 10/16/01: page 2 added date revision for pin configuration pages 4, 5 & 7 removed industrial temp values and column headings for 15 & 25ns speeds from dc and ac electrical characteristics page 9 removed industrial temp offering from 15 & 25ns ordering information added industrial temp footnote to ordering information pages 1 & 9 replaced tm logo with ? logo 04/04/06: page 1 added green availability to features page 9 added green indicator to ordering information 12/11/08: page 9 removed "idt" from orderable part number 08/18/14: page 9 added tape and reel to ordering information page 2 & 9 the package codes pn84-1 & j52-1 changed to pn84 & j52 respectively to match standard package codes notes : 1. industrial temperature: for other speeds, packages and powers contact your sales office. 2. green parts avaliable. for specific speeds, packages and powers contact your local sales office. 2528 drw 11 xxxx a 999 a a device type power speed package process/ temperature range blank i (1) pf j 12 15 20 25 commercial (0c to +70c) industrial (-40c to +85c) 64-pin tqfp (pn64) 52-pin plcc (j52) speed in nanoseconds commercial only commercial only commercial & industrial commercial only s standard power 7014 36k (4k x 9-bit) dual-port ram a g (2) green blank 8 tube or tray tape and reel a
idt7014s high-speed 4k x 9 dual-port static ram industrial and commercial temperature ranges 10 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com the idt logo is a registered trademark of integrated device technology, inc. datasheet document history (con't) 03/16/16: page 2 changed diagram for the pn64 pin configuration by rotating package pin labels and pin numbers 90 degrees counter clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1 removed the pn64 chamfer and aligned the top and bottom pin labels in the standard direction added the idt logo to the pn64 pin configurations and changed the text to be in alignment with new diagram marking specs removed the date revision indicator for each pin configuration updated footnote references for pn64 pin configuration page 4 figuire 3 typical output derating graph, corrected a typo
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